1. Field of the Invention
The present invention relates to a method for forming an inlaid interconnect that has low wiring resistance, high electromigration (EM) resistance, and high reliability.
2. Description of the Related Art
As miniaturization of LSIs has advanced, interconnection RC delay time has increased significantly. To address this, Cu inlaid interconnects having low wiring resistance have started being used instead of conventionally used Al interconnects. Typically, Cu inlaid interconnects are more resistant to EM than Al interconnects. Nevertheless, as interconnects have been miniaturized, the density of current passing through the interconnects has increased, and hence EM resistance needs to be increased even in Cu interconnects.
A known method for increasing the EM resistance of a Cu inlaid interconnect is to diffuse an impurity element (typically a metal element) into the Cu inlaid interconnect. For example, a Cu alloy seed layer to which an impurity element has been added is used as a seed layer underlying a Cu plating, and after the Cu plating layer is formed on the Cu alloy seed layer, a heat treatment is performed to diffuse the impurity element from the Cu alloy seed layer into the Cu plating layer.
However, the impurity element diffusion from the Cu alloy seed layer into the Cu plating layer is diffusion occurring between the films both made of Cu. Thus, there is no energy barrier to the impurity element, allowing the impurity element to diffuse into the entire Cu plating layer. As a result, the resistivity of the Cu interconnect is increased, causing the RC delay time of the interconnect to be increased.
Also, when the Cu alloy seed layer is formed using a sputtering apparatus and then transferred to a plating apparatus to form the Cu plating layer, the surface of the Cu alloy seed layer is exposed to the atmosphere. This causes the impurity element added to the Cu alloy seed layer to be oxidized to form an oxide layer on the surface of the Cu alloy seed layer, resulting in a reduction in the adhesion strength between the Cu alloy seed layer and the Cu plating layer.
In view of these problems, a technique is described in Japanese Laid-Open Publication No. 2004-47846 in which EM resistance is increased by diffusing an impurity element into a Cu plating layer while the adhesion between the Cu plating layer and a Cu seed layer is maintained.
FIGS. 8A to 8C are cross-sectional views illustrating process steps in the method for forming a Cu inlaid interconnect described in Japanese Laid-Open Publication No. 2004-47846.
First, as shown in FIG. 8A, after a groove 102 for an inlaid interconnect is formed in an insulating layer 101 formed on a silicon substrate 100, a barrier metal layer (typically an alloy barrier metal layer) 103, to which an impurity element is added, and a Cu seed layer 104 are consecutively formed on the insulating layer 101 in a sputtering apparatus so as to cover the side walls and bottom of the groove 102. Then, as shown in FIG. 8B, a Cu plating layer 105 is formed on the Cu seed layer 104 so as to fill the groove 102.
Next, as shown in FIG. 8C, part of the Cu plating layer 105, part of the Cu seed layer 104, and part of the alloy barrier metal layer 103 located on the insulating layer 101 are removed so as to expose the surface of the insulating layer 101, thereby filling the groove 102 with the Cu plating layer 105. Thereafter, a heat treatment is performed to diffuse the impurity element existing in the alloy barrier metal layer 103 into the Cu plating layer 105.
In this manner, when the impurity element is diffused from the alloy barrier metal layer 103 into the Cu plating layer 105, a energy barrier to the diffusion of the impurity element is formed at the interface between the alloy barrier metal layer 103 and the Cu plating layer 105 (including the Cu seed layer 104), thereby suppressing the diffusion into the Cu plating layer 105. In addition, the consecutive formation of the alloy barrier metal layer 103 and the Cu seed layer 104 in the sputtering apparatus prevents exposure of the impurity element added to the alloy barrier metal layer 103 to the atmosphere and the resultant oxidation thereof. Accordingly, an inlaid Cu interconnect in which increase in wiring resistivity is suppressed and adhesion is maintained is formed.